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vhdl & system verilog

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   Hi All,

I have a very basic qn - jus picking up system. verilog -> if the testbench is in system verilog
and the top level is in vhdl - will both the modules be able to talk to each other?

Many Thanks in advance,
indeb


Originally posted in cdnusers.org by indeb
Parents

  • Posted By indeb on 3/21/2007 8:46 PM
    Hi Ajeetha

    sorry jus a couple of qns -> what do you mean by LRM, NC, mixed mode sim - mixed mode simulator? co sim?
    I am using modelsim - for simulation - but not too sure about the model building - when I buid the model - what is actually executing the code - I am on vnc server - I use modelsim to trace the signals - debbugging - but not too sure on how the
    codes are being built into a model - any insight?

    Thanks a mil!
    indeb
    LRM - Language Reference Manual
    NC - NCSIM (www.cadence.com)

    Do google search to learn more on these.

    Regards
    Ajeetha, CVC
    www.noveldv.com


    Originally posted in cdnusers.org by ajeetha
Reply

  • Posted By indeb on 3/21/2007 8:46 PM
    Hi Ajeetha

    sorry jus a couple of qns -> what do you mean by LRM, NC, mixed mode sim - mixed mode simulator? co sim?
    I am using modelsim - for simulation - but not too sure about the model building - when I buid the model - what is actually executing the code - I am on vnc server - I use modelsim to trace the signals - debbugging - but not too sure on how the
    codes are being built into a model - any insight?

    Thanks a mil!
    indeb
    LRM - Language Reference Manual
    NC - NCSIM (www.cadence.com)

    Do google search to learn more on these.

    Regards
    Ajeetha, CVC
    www.noveldv.com


    Originally posted in cdnusers.org by ajeetha
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