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Wand Wires to be driven by Program Block and Module block

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Hi All,

I have a design that have some bidirectional signals, driven one side by Verilog Module, next side by SV testbench.
But signals should have a functionality of wand (wire-and) type only
Both are interacting through SV Interfaces only.

Three combinations I tried:

  1. from SV testbenchn,  if I decleare  logic a , b , it give errors inout port must be a net type
  2. when I declare them as  wand a,b, and it give error while driving them through TB, it give error usage of 'intf_inst.b' inconsistent with 'net' object.
  3. when I declare with input and output types, it give error blocking and non-blocking assignments to heirarchical references in a program block are illegal
What's the solution?

Regards
Mayank

Sample code is as such

interface intf( input logic clock);
wand a,b;

modport port (inout a,b);

endinterface

program main (intf intf_inst);
 int count =0;
initial begin
    while (1) begin
    #10;
        intf_inst.b = 1'b1;
        count = count +1;
        if (count >1000) $finish;
    end
    
end
endprogram

module top;
    reg data_value, clock;
    intf intf_inst (clock);
    main m(intf_inst.port);
     assign  intf_inst.a = data_value;

    initial begin
          clock =0;
        forever begin
              #10 clock = ~clock;
        end
    end
endmodule


Originally posted in cdnusers.org by mayank
Parents

  • Even though this is SystemVerilog, you still have to deal with some of the restrictions enforced by the underlying Verilog language itself. In that language, you cannot make behavioral assignments directly to a "net" type. A net type like wand can have multiple drivers. You can only make behavioral assignments to a single driver of the net. Then Verilog will resolve the multiple drivers into their final value.

    interface intf( input logic clock);
    wand a,b;
    logic b_driver;

    assign b = b_driver;

    modport port (inout a,b);

    endinterface

    program main (intf intf_inst);
    int count =0;
    initial begin
    while (1) begin
    #10;
    intf_inst.b_driver = 1'b1;

    If you truely wanted the port to be bidirectional, you might want to put a control on the behavioral driver you are creating:

    interface intf( input logic clock);
    wand a,b;
    logic b_driver,b_ctrl;

    modport port (inout a,b);

    assign b = b_ctrl ? b_driver : 'bz;

    endinterface


    Originally posted in cdnusers.org by TAM
Reply

  • Even though this is SystemVerilog, you still have to deal with some of the restrictions enforced by the underlying Verilog language itself. In that language, you cannot make behavioral assignments directly to a "net" type. A net type like wand can have multiple drivers. You can only make behavioral assignments to a single driver of the net. Then Verilog will resolve the multiple drivers into their final value.

    interface intf( input logic clock);
    wand a,b;
    logic b_driver;

    assign b = b_driver;

    modport port (inout a,b);

    endinterface

    program main (intf intf_inst);
    int count =0;
    initial begin
    while (1) begin
    #10;
    intf_inst.b_driver = 1'b1;

    If you truely wanted the port to be bidirectional, you might want to put a control on the behavioral driver you are creating:

    interface intf( input logic clock);
    wand a,b;
    logic b_driver,b_ctrl;

    modport port (inout a,b);

    assign b = b_ctrl ? b_driver : 'bz;

    endinterface


    Originally posted in cdnusers.org by TAM
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