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Reg : problem with reg declaration in IUS58

Hi all, I have declared a data member as reg. when i use it in an assign statement, I am supposed to get an error.Now 1. If i use the +sv switch i am not getting an error. 2. its showing an error if i do not use the +sv switch,which is as expected. I am using cadence IUS58, please clarify on this. thanks Manmohan

Originally posted in cdnusers.org by mssajwan

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archive over 18 years ago

Hi Davy,

I have used the declaration inside a module

module test();
reg a,b;

assign a = b ? 1 : 0 ;

endmodule

in this code with +sv command line option its not giving me an error.

Originally posted in cdnusers.org by mssajwan
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archive over 18 years ago

Hi Davy,

I have used the declaration inside a module

module test();
reg a,b;

assign a = b ? 1 : 0 ;

endmodule

in this code with +sv command line option its not giving me an error.

Originally posted in cdnusers.org by mssajwan
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