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Generating Code Coverage for SV Verification Environment

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Hi,

How to calculate Code Coverage for a System Verilog Verification Environment?

At present, i am not using a DUT. I am taking two instances of my Verfn. Environment for verification.

I am able to generate functional coverage data but for code coverage how should i proceed??

Can i have a specific flow to generate and calculate code coverage for the Environment w/o DUT.




Regards

Jagvin

 


Originally posted in cdnusers.org by jagvinder
Parents

  • Hi Jagvin.

    Can you see if this thread answers your question?
    http://www.cdnusers.org/Forums/tabid/52/forumid/66/postid/4642/view/topic/Default.aspx

    If not, maybe you can be a bit more specific about what you're trying to do.
    Normally you can treat the TB as the "DUT" for coverage purposes, so you can do code coverage for static structures like modules.

    Steve.


    Originally posted in cdnusers.org by stephenh
Reply

  • Hi Jagvin.

    Can you see if this thread answers your question?
    http://www.cdnusers.org/Forums/tabid/52/forumid/66/postid/4642/view/topic/Default.aspx

    If not, maybe you can be a bit more specific about what you're trying to do.
    Normally you can treat the TB as the "DUT" for coverage purposes, so you can do code coverage for static structures like modules.

    Steve.


    Originally posted in cdnusers.org by stephenh
Children
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