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Generating Code Coverage for SV Verification Environment

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Hi,

How to calculate Code Coverage for a System Verilog Verification Environment?

At present, i am not using a DUT. I am taking two instances of my Verfn. Environment for verification.

I am able to generate functional coverage data but for code coverage how should i proceed??

Can i have a specific flow to generate and calculate code coverage for the Environment w/o DUT.




Regards

Jagvin

 


Originally posted in cdnusers.org by jagvinder
Parents

  • Hi Ajeetha,

    I have a module based environment. I have tried few steps given in NCSIM user guide and ICCR guide for code coverage.

    But still, i am unable to generate cov_work directory and the files for code coverage.

    Can u please let me know which steps i shold take for this. I mean i have a "top", so to calculate its code coverage should i proceed with (1) Compilation (2) Elaboration (3) Simulation

    What different commands i can use to create cov_work and code coverage files.

    Thanx

    Regards

    Jagvinder





    Originally posted in cdnusers.org by jagvinder
Reply

  • Hi Ajeetha,

    I have a module based environment. I have tried few steps given in NCSIM user guide and ICCR guide for code coverage.

    But still, i am unable to generate cov_work directory and the files for code coverage.

    Can u please let me know which steps i shold take for this. I mean i have a "top", so to calculate its code coverage should i proceed with (1) Compilation (2) Elaboration (3) Simulation

    What different commands i can use to create cov_work and code coverage files.

    Thanx

    Regards

    Jagvinder





    Originally posted in cdnusers.org by jagvinder
Children
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