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Generating Code Coverage for SV Verification Environment

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Hi,

How to calculate Code Coverage for a System Verilog Verification Environment?

At present, i am not using a DUT. I am taking two instances of my Verfn. Environment for verification.

I am able to generate functional coverage data but for code coverage how should i proceed??

Can i have a specific flow to generate and calculate code coverage for the Environment w/o DUT.




Regards

Jagvin

 


Originally posted in cdnusers.org by jagvinder
Parents

  • Hi Ajeetha & Steve,

    Thanks a lot.
    The command "ncelan -coverage " worked.

    Actually i had to use -cov58 as i am using IUS 6.1.

    I used the command "ncelab -cov58 -coverage all " and it created coverage database for all the coverages after simulation.


    Thanx once again.

    Regards

    Jagvinder


    Originally posted in cdnusers.org by jagvinder
Reply

  • Hi Ajeetha & Steve,

    Thanks a lot.
    The command "ncelan -coverage " worked.

    Actually i had to use -cov58 as i am using IUS 6.1.

    I used the command "ncelab -cov58 -coverage all " and it created coverage database for all the coverages after simulation.


    Thanx once again.

    Regards

    Jagvinder


    Originally posted in cdnusers.org by jagvinder
Children
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