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What do you think of the new OVM announcement?

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Hello,

In case you missed the biggest news affecting SystemVerilog adoption, here it is. Today, Mentor and Cadence announced an intent to jointly develop a SystemVerilog methodology that is truly portable across multiple simulators and provides a very capable library for building highly automated and reusable verification environments.

Here's the full press release ->

http://biz.yahoo.com/bw/070816/20070816005160.html?.v=1

Curious to see what users think of this new development.

Umer Yousafzai

CoreComp Senior Technical Lead

Cadence


Originally posted in cdnusers.org by umer
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