What do you think of the new OVM announcement?

I liked it. I think it will move SV forward more quickly and will help with the logistics from a users perspective.

Originally posted in cdnusers.org by bryan

We think it is a positive step that will encourage more current VHDL/Verilog users to consider adopting SystemVerilog as their verification language.

As independent providers of SystemVerilog language and methodology training, one of our biggest headaches over the past couple of years has been producing training materials that are applicable to and work with multiple vendor tools. We have also found it necessary to create methodology-specific SystemVerilog courses for both AVM and URM. If the OVM announcement means that IUS and QuestaSim will both support a similar subset of the  p1800 standard in in the near future, this could make our life a whole lot easier.

We have been told that OVM will be backwards-compatible with AVM 3.1 and URM 6.2. I haven't seen the source code yet but this seems to imply an implementation of URM based on the AVM classes? I have a few other questions related to the implementation:

1) How much of the current URM will become part of OVM?
2) Will OVM support the same set of foreign languane interfaces (e.g. will integrating an e TB module change/still work)?
3) Will development of non SV modules (e.g. e) continue alongside OVM?
4) When is IUS 6.2 due?

Regards,
Dave

Originally posted in cdnusers.org by dl_doulos

Hi David,

We are actively working with Mentor on the technical details, but in response to your questions:

1) How much of the current URM will become part of OVM?

All of the current URM SystemVerilog Class-based methodology will become part of OVM, so existing URM users will be able to seamlessly transition to OVM. More importantly, any URM VIP that is developed will be interoperable with the rest of the world that adopts OVM.

2) Will OVM support the same set of foreign languane interfaces (e.g. will integrating an e TB module change/still work)?

Cadence and Mentor have both been providing multi-language verification tool & methodology support and we definitely plan to make sure that OVM will provide at least the same level of support as Mentor provides today with SystemC and Cadence provides with e and SystemC. This will enable users to reuse their SystemVerilog VIP to connect to both RTL and SystemC TLM models, and enable plug & play VIP between OVM SystemVerilog VIP and eRM VIP.

3) Will development of non SV modules (e.g. e) continue alongside OVM?

The short answer is yes. As you know, there is a lot more to verification beyond SystemVerilog testbenches. At Cadence we have developed the Incisive Plan to Closure Methodology (IPCM) which is a complete methodology spanning block to system level verification, from verification planning to coverage closure, and includes assertions, coverage-driven testbench reuse, and SystemC TLM, HW/SW co-verification, and Hardware-assisted system verification. URM has been a key component of IPCM for developing reusable SystemVerilog and e coverage-driven testbenches, and since OVM will be a superset of URM, we fully plan to make sure that OVM fits within IPCM. To your specific question about e, we continue to evolve the e Reuse Methodology, and we will make sure that eRM VIP will plug & play with SystemVerilog OVM VIP.

4) When is IUS 6.2 due?

6.2 is planned to be release in November.

Originally posted in cdnusers.org by mstellfox

Hello,

Why not synopsys?

Regards,
Roger

Originally posted in cdnusers.org by witlox

Why not synopsys?

Hi Roger,
OVM will be truly open-source and based 100% on IEEE1800, so Synopsys and any other vendor that supports the SystemVerilog standard will be able to access and run OVM and OVM-based VIP.

Originally posted in cdnusers.org by mstellfox