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What do you think of the new OVM announcement?

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Hello,

In case you missed the biggest news affecting SystemVerilog adoption, here it is. Today, Mentor and Cadence announced an intent to jointly develop a SystemVerilog methodology that is truly portable across multiple simulators and provides a very capable library for building highly automated and reusable verification environments.

Here's the full press release ->

http://biz.yahoo.com/bw/070816/20070816005160.html?.v=1

Curious to see what users think of this new development.

Umer Yousafzai

CoreComp Senior Technical Lead

Cadence


Originally posted in cdnusers.org by umer
Parents

  • We think it is a positive step that will encourage more current VHDL/Verilog users to consider adopting SystemVerilog as their verification language.

    As independent providers of SystemVerilog language and methodology training, one of our biggest headaches over the past couple of years has been producing training materials that are applicable to and work with multiple vendor tools. We have also found it necessary to create methodology-specific SystemVerilog courses for both AVM and URM. If the OVM announcement means that IUS and QuestaSim will both support a similar subset of the  p1800 standard in in the near future, this could make our life a whole lot easier.

    We have been told that OVM will be backwards-compatible with AVM 3.1 and URM 6.2. I haven't seen the source code yet but this seems to imply an implementation of URM based on the AVM classes? I have a few other questions related to the implementation:

    1) How much of the current URM will become part of OVM?
    2) Will OVM support the same set of foreign languane interfaces (e.g. will integrating an e TB module change/still work)?
    3) Will development of non SV modules (e.g. e) continue alongside OVM?
    4) When is IUS 6.2 due?

    Regards,
    Dave


    Originally posted in cdnusers.org by dl_doulos
Reply

  • We think it is a positive step that will encourage more current VHDL/Verilog users to consider adopting SystemVerilog as their verification language.

    As independent providers of SystemVerilog language and methodology training, one of our biggest headaches over the past couple of years has been producing training materials that are applicable to and work with multiple vendor tools. We have also found it necessary to create methodology-specific SystemVerilog courses for both AVM and URM. If the OVM announcement means that IUS and QuestaSim will both support a similar subset of the  p1800 standard in in the near future, this could make our life a whole lot easier.

    We have been told that OVM will be backwards-compatible with AVM 3.1 and URM 6.2. I haven't seen the source code yet but this seems to imply an implementation of URM based on the AVM classes? I have a few other questions related to the implementation:

    1) How much of the current URM will become part of OVM?
    2) Will OVM support the same set of foreign languane interfaces (e.g. will integrating an e TB module change/still work)?
    3) Will development of non SV modules (e.g. e) continue alongside OVM?
    4) When is IUS 6.2 due?

    Regards,
    Dave


    Originally posted in cdnusers.org by dl_doulos
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