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Help needed in creating URM using SV

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Hello friends!
I'm facing a problem while creating my Verification IP using SV language in URM environment.
Right now, I'm just trying to up my master agent with these files:

package.sv
dut_interface.sv
master_sequence_driver.sv
master_interface.sv
master_bfm.sv
master_monitor.sv
master_agent.sv
dut_dummy.v
dut_wrap.sv
bus_interface.sv

I got two errors"An interface connection must be connected to verilog parent" and "An interface port declaration must be connected".....

I couldn't able to go further....can anyone help me in this regards!?

Thanks in advance!
Regards,
Jalli


Originally posted in cdnusers.org by jaally
Parents

  • Hi Jalli.

    You get these messages if you have not connected the SV interfaces correctly to your agent or DUT.
    If for example you DUT has a port declared as an interface, it must be connected to an interface of the same type.

    Without seeing your files it's hard to pinpoint the exact error, but I suggest you double check the connections from you top file going into the agent and DUT instances.

    You can send me the files if you don't manage to resolve it : stephenh cadence.com

    By the way, when you get an error message that you don't understand, try looking it up using the nchelp command. This usually gives some more details about the problem and how to solve it. For the two messages you described I pasted the nchelp commands and the output:

    [sve/main] $ nchelp ncelab CUINMD
    nchelp: 06.11-s003: (c) Copyright 1995-2007 Cadence Design Systems, Inc.
    ncelab/CUINMD =
    This is an incompatible connection. A Verilog interface must be connected
    to a port of a Verilog instance. All other languages and connection
    types are disallowed.

    [sve/main] $ nchelp ncelab CUIMBC
    nchelp: 06.11-s003: (c) Copyright 1995-2007 Cadence Design Systems, Inc.
    ncelab/CUIMBC = An interface port declaration may not be left unconnected.
    [sve/main] $


    Originally posted in cdnusers.org by stephenh
Reply

  • Hi Jalli.

    You get these messages if you have not connected the SV interfaces correctly to your agent or DUT.
    If for example you DUT has a port declared as an interface, it must be connected to an interface of the same type.

    Without seeing your files it's hard to pinpoint the exact error, but I suggest you double check the connections from you top file going into the agent and DUT instances.

    You can send me the files if you don't manage to resolve it : stephenh cadence.com

    By the way, when you get an error message that you don't understand, try looking it up using the nchelp command. This usually gives some more details about the problem and how to solve it. For the two messages you described I pasted the nchelp commands and the output:

    [sve/main] $ nchelp ncelab CUINMD
    nchelp: 06.11-s003: (c) Copyright 1995-2007 Cadence Design Systems, Inc.
    ncelab/CUINMD =
    This is an incompatible connection. A Verilog interface must be connected
    to a port of a Verilog instance. All other languages and connection
    types are disallowed.

    [sve/main] $ nchelp ncelab CUIMBC
    nchelp: 06.11-s003: (c) Copyright 1995-2007 Cadence Design Systems, Inc.
    ncelab/CUIMBC = An interface port declaration may not be left unconnected.
    [sve/main] $


    Originally posted in cdnusers.org by stephenh
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