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Help needed in creating URM using SV

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Hello friends!
I'm facing a problem while creating my Verification IP using SV language in URM environment.
Right now, I'm just trying to up my master agent with these files:

package.sv
dut_interface.sv
master_sequence_driver.sv
master_interface.sv
master_bfm.sv
master_monitor.sv
master_agent.sv
dut_dummy.v
dut_wrap.sv
bus_interface.sv

I got two errors"An interface connection must be connected to verilog parent" and "An interface port declaration must be connected".....

I couldn't able to go further....can anyone help me in this regards!?

Thanks in advance!
Regards,
Jalli


Originally posted in cdnusers.org by jaally
Parents

  • Hi Jally.

    I just replied to your mail with some more info. For the record, because you have only compiled the agent, and no env or testbench to instantiate the agent, the agent's interface is left unconnected, which is illegal in SystemVerilog.

    You should refer to the URM docs, and also the vr_xbus example that comes wit IPCM.
    You can find the vr_xbus example files under the IPCM installation, like this:
      IPCM/6.11/ipcm/urm_lib/sv_mb_ex_lib/vr_xbus

    Normally your testbench hierarchy would look something like this:

    sve   (top module)
     |- dut_if   (instance of dut interface)
     |- dut_wrapper  (instance)
     |     |- dut   (the real dut)
     |- sips_ahb_env  (instance of the AHB env)
     |    |- sips_ahb_master_agent
     |    |    |- sips_ahb_master_monitor
     |    |    |- sips_ahb_master_driver
     |    |    |- sips_ahb_master_bfm
     |    |- sips_ahb_slave_agent
     |    |    |- (structure as per master agent)
     |- any_other_interface_env
          |- any_other_interface_master_agent
          |     |- any_other_interface_master_monitor
          |     |- ...
          |- any_other_interface_slave_agent
     


    Originally posted in cdnusers.org by stephenh
Reply

  • Hi Jally.

    I just replied to your mail with some more info. For the record, because you have only compiled the agent, and no env or testbench to instantiate the agent, the agent's interface is left unconnected, which is illegal in SystemVerilog.

    You should refer to the URM docs, and also the vr_xbus example that comes wit IPCM.
    You can find the vr_xbus example files under the IPCM installation, like this:
      IPCM/6.11/ipcm/urm_lib/sv_mb_ex_lib/vr_xbus

    Normally your testbench hierarchy would look something like this:

    sve   (top module)
     |- dut_if   (instance of dut interface)
     |- dut_wrapper  (instance)
     |     |- dut   (the real dut)
     |- sips_ahb_env  (instance of the AHB env)
     |    |- sips_ahb_master_agent
     |    |    |- sips_ahb_master_monitor
     |    |    |- sips_ahb_master_driver
     |    |    |- sips_ahb_master_bfm
     |    |- sips_ahb_slave_agent
     |    |    |- (structure as per master agent)
     |- any_other_interface_env
          |- any_other_interface_master_agent
          |     |- any_other_interface_master_monitor
          |     |- ...
          |- any_other_interface_slave_agent
     


    Originally posted in cdnusers.org by stephenh
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