Help needed in creating URM using SV

Hello friends!
I'm facing a problem while creating my Verification IP using SV language in URM environment.
Right now, I'm just trying to up my master agent with these files:

package.sv
dut_interface.sv
master_sequence_driver.sv
master_interface.sv
master_bfm.sv
master_monitor.sv
master_agent.sv
dut_dummy.v
dut_wrap.sv
bus_interface.sv

I got two errors"An interface connection must be connected to verilog parent" and "An interface port declaration must be connected".....

I couldn't able to go further....can anyone help me in this regards!?

Thanks in advance!
Regards,
Jalli