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Differences b/w logic , reg & wire

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hi,

1.      i  know the differences between reg & wire...but i what to know the differences between logic , reg & wire clearly.

2.     When iam writing code in systemverilog using URM ..... i got a simple bug.. which iam pasting below & please let me know where to use reg , wire & logic in systemverilog coding.....


  
      

ncelab: *W,ENUMERR (./sv_module/sips_apb_env.sv,53|66): This
assignment is a violation of SystemVerilog strong typing rules for
enumeration datatypes.
            .PWRITE(dut_if.PWRITE),
                  |
ncelab: *E,ICDPAV (./sv_module/sips_apb_dut_wrap.sv,25|19): Illegal combination
of driver and procedural assignment to variable dut_if.PWRITE detected.
            .PADDR(dut_if.PADDR),
                 |
ncelab: *E,ICDPAV (./sv_module/sips_apb_dut_wrap.sv,26|18): Illegal combination
of driver and procedural assignment to variable dut_if.PADDR detected.
            .PWDATA(dut_if.PWDATA),      


... Raghavendra


Originally posted in cdnusers.org by raghavendrap
Parents

  • ncelab: *W,ENUMERR (./sv_module/sips_apb_env.sv,53|66): This
    assignment is a violation of SystemVerilog strong typing rules for
    enumeration datatypes.
    .PWRITE(dut_if.PWRITE),



    You need to show us the declaration of:

    PWRITE inside the DUT and
    dut_if.PWRITE



    ncelab: *E,ICDPAV (./sv_module/sips_apb_dut_wrap.sv,25|19): Illegal combination
    of driver and procedural assignment to variable dut_if.PWRITE detected.



    Again we need full declaration that shows:

    1. Data type
    2. Direction (I/O/IO)

    to comment properly. From the clear error message it is clear that you have a "procedural assignment" - say inside task/function/initial PWRITE and perhaps a "net" connection from a block beneath.

    Show us full code to help better. If it is too many lines, consider posting a tar ball or send via email ajeetha <> gmail.com

    Interestingly I was doing some revamp of our (CVC, www.noveldv.com) SystemVerilog training material this week and found similar examples that we show during our classes.

    Regards
    Ajeetha, CVC
    www.noveldv.com


    Originally posted in cdnusers.org by ajeetha
Reply

  • ncelab: *W,ENUMERR (./sv_module/sips_apb_env.sv,53|66): This
    assignment is a violation of SystemVerilog strong typing rules for
    enumeration datatypes.
    .PWRITE(dut_if.PWRITE),



    You need to show us the declaration of:

    PWRITE inside the DUT and
    dut_if.PWRITE



    ncelab: *E,ICDPAV (./sv_module/sips_apb_dut_wrap.sv,25|19): Illegal combination
    of driver and procedural assignment to variable dut_if.PWRITE detected.



    Again we need full declaration that shows:

    1. Data type
    2. Direction (I/O/IO)

    to comment properly. From the clear error message it is clear that you have a "procedural assignment" - say inside task/function/initial PWRITE and perhaps a "net" connection from a block beneath.

    Show us full code to help better. If it is too many lines, consider posting a tar ball or send via email ajeetha <> gmail.com

    Interestingly I was doing some revamp of our (CVC, www.noveldv.com) SystemVerilog training material this week and found similar examples that we show during our classes.

    Regards
    Ajeetha, CVC
    www.noveldv.com


    Originally posted in cdnusers.org by ajeetha
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