hi,1. i know the differences between reg & wire...but i what to know the differences between logic , reg & wire clearly.2. When iam writing code in systemverilog using URM ..... i got a simple bug.. which iam pasting below & please let me know where to use reg , wire & logic in systemverilog coding.....
I think it would help the discussion if you would add the following info:1. The declaration for dut_if.PWRITE2. The port declaration for .PWRITE
ncelab: *W,ENUMERR (./sv_module/sips_apb_env.sv,53|66): Thisassignment is a violation of SystemVerilog strong typing rules forenumeration datatypes. .PWRITE(dut_if.PWRITE),
ncelab: *E,ICDPAV (./sv_module/sips_apb_dut_wrap.sv,25|19): Illegal combinationof driver and procedural assignment to variable dut_if.PWRITE detected.
thanks for your cooperation in helping me Tam.. i have declared as dut.v file....ouput reg PWRITE dut_interface.sv...logic PWRITE dut_wrap.sv--------- .PWRITE(dut_if.PWRITE) dut_if is the dut interface name..........
I've run a couple of tests using an interface, an always block and a submodule connection and I can't duplicate all of the behavior that you are seeing. :-(One thing that has been explained to me that the SystemVerilog has two properties associated with a signal, its "type" and its "kind." The "kind" is the familiar Verilog "reg", "var" or "wire". The "type" is the data type, 4-state "logic", 2-state "bit", integer and real. You can leave out the "kind", as long as you have specified the "type". But if you do, then "reg" is assumed."logic PWRITE" is thus the same as "reg logic PWRITE".In SystemVerilog, you are allowed one continuous assignment to a "reg", so you can connect that interface signal to a submodule's port. But if you also try to drive it using a behavioral assignment or connect it to a second port, you will get an error. So I can easily get the tool to complain about different combinations of drivers on a PWRITE signal that is implicitly declared as a "reg". But I can't quite get it to complain in the same way that you are seeing, so I can't really be sure what you might have done.See what happens if you try declaring the signal as a wire.wire logic PWRITE;Or go thru your assignments and connections to that signal and make sure that they are all consistant with a "reg" kind of signal.
This is not quite correct.In SystemVerilog, logic and reg are both data types. In fact, they are the same data type.So 'logic PWRITE' is like 'var logic PWRITE' and 'reg PWRITE' is like 'var reg PWRITE'.