Stats

  • Locked Locked
  • Replies 7
  • Subscribers 64
  • Views 5291
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Differences b/w logic , reg & wire

archive

hi,

1.      i  know the differences between reg & wire...but i what to know the differences between logic , reg & wire clearly.

2.     When iam writing code in systemverilog using URM ..... i got a simple bug.. which iam pasting below & please let me know where to use reg , wire & logic in systemverilog coding.....


  
      

ncelab: *W,ENUMERR (./sv_module/sips_apb_env.sv,53|66): This
assignment is a violation of SystemVerilog strong typing rules for
enumeration datatypes.
            .PWRITE(dut_if.PWRITE),
                  |
ncelab: *E,ICDPAV (./sv_module/sips_apb_dut_wrap.sv,25|19): Illegal combination
of driver and procedural assignment to variable dut_if.PWRITE detected.
            .PADDR(dut_if.PADDR),
                 |
ncelab: *E,ICDPAV (./sv_module/sips_apb_dut_wrap.sv,26|18): Illegal combination
of driver and procedural assignment to variable dut_if.PADDR detected.
            .PWDATA(dut_if.PWDATA),      


... Raghavendra


Originally posted in cdnusers.org by raghavendrap
Parents Reply Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.