array initialization [1a] (system-verilog)

Using the IUS 5.83 version, I'm trying to
compile these simple SV code lines:

parameter    ports_num                  = 4;      // ports number

integer px_num[ports_num-1:0];    // pixel num x port


initial
begin
  px_num[ports_num-1:0] = { 4'h8, 4'h8, 4'h6, 4'h6 };
end


and I got the following errors

Compiling SHM component...
file: /IPREUSE/DATABASE/INTERNAL/DIG/INPROGRESS/gborgo/simd_A0_a/config/../generic/rtl/svlog/shm.v
  px_num[ports_num-1:0] = { 4'h8, 4'h8, 4'h6, 4'h6 };
       |
ncvlog: *E,NOPSOM (/IPREUSE/DATABASE/INTERNAL/DIG/INPROGRESS/gborgo/simd_A0_a/config/../generic/rtl/svlog/shm.v,117|7): part-select or indexed part-select cannot be applied to memory [4.2.2(IEEE)].
        module simd.shm:v
                errors: 1, warnings: 0



Is it a problem of the IUS 5.83 version ?

Thanks
BR
Giampiero Borgonovo