Stats

  • Locked Locked
  • Replies 2
  • Subscribers 64
  • Views 13263
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Verification with system verilog

archive

Verification environment implementation with system verilog.


Originally posted in cdnusers.org by jagannadh.sv

  • The question is : I am real satisfied user of IUS, now i am upgrading my self with system verilog, i have licensed version of IUS5.4, I started writing small programs and try running in IUS5.4 which i was using it for verilog before. when i started learning some programs which has classses, and try to compile, it is compiling fine but not not simulation showing that "This needs a seperate license", Does it really need a seperate license or any other solution?


    Originally posted in cdnusers.org by jagannadh.sv

  • Hi jagannadh.sv

    Could you please post the log file and your test bench writing in system verilog?
    Cadence IUS low version can’t support the some features of system verilog.These
    features could find in the document of the tool installing directory.

    shawn lieu


    Originally posted in cdnusers.org by shawn-1

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.