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looking for SV testbench command file Hiisequencer code

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I'm working on exsiting test bench , and i need to modify it.
At the moment all our tests are running in serial one after the other .
 
We want to run tests in a different way. To be able to kick tests using “control file” that will be able to
Run test in serial or parallel (fork/join) , test in a loop or  have a “name” of test with input variables (like SEED for random run).
 
My question is , is there SystemVerilog (AVM) open source code we can use of a Sequencer that can read external files and kick test in similar manner ?
Or something similar that can be a good starting point ?
 
 
It may look like this :
 
Sync = 0, wait = 1
test  0  test1   0
test   1  test2   1
 
Sync and wait are controls to the sequencer to run the test in specific manner . and same for values after the test name.
 Thanks Dan
 


Originally posted in cdnusers.org by danny_isr
Parents

  • Hi Danny,

    similarly you can use $value$plusargs to pass the sequence.
    According to which your testcases you can execute.

    As per parallel execution is concerned you can pass command for that with testcase name to be executed in parallel through same
    $value$plusargs on command line.(both testcase thread should not overlap.).


    Originally posted in cdnusers.org by divyeshg
Reply

  • Hi Danny,

    similarly you can use $value$plusargs to pass the sequence.
    According to which your testcases you can execute.

    As per parallel execution is concerned you can pass command for that with testcase name to be executed in parallel through same
    $value$plusargs on command line.(both testcase thread should not overlap.).


    Originally posted in cdnusers.org by divyeshg
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