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check if 2 signals are connected :

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hello,

i'd like to check if 2 verilog signals are connected (of any kind - wire, reg , etc ...). 
the trivial case is when there's a direct dependency (like A = ~B ) and very easy to trace. 
but take a look at the following pseudo code: here you can notice that D in indirectly influenced by A. although it's easy to trace it in this example, there can be very large code blocks, with many distinguished modules, each written in different file... what make it much more difficult to trace  



clk = A and ~B
always (clk rise) 
   if (X==0)    
      D = C;
   else 
      D = 0; 
end


thanks !!!


Originally posted in cdnusers.org by zcabeli11
Parents

  • i see that my example wasn't recored, so i type it again to illustrate my problem:


    < code >
    A = B|C&D;

    always (posedge A)
    val <= 3'h0;

    < /code >

    in this example i'm seeking to find a simple method that check connectivity (for example between C and val).
    of course that i'm aiming toward much more complex modules which have many code lines, and the connection between
    2 end points may go through a lot of intermediators .



    Originally posted in cdnusers.org by zcabeli11
Reply

  • i see that my example wasn't recored, so i type it again to illustrate my problem:


    < code >
    A = B|C&D;

    always (posedge A)
    val <= 3'h0;

    < /code >

    in this example i'm seeking to find a simple method that check connectivity (for example between C and val).
    of course that i'm aiming toward much more complex modules which have many code lines, and the connection between
    2 end points may go through a lot of intermediators .



    Originally posted in cdnusers.org by zcabeli11
Children
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