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check if 2 signals are connected :

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hello,

i'd like to check if 2 verilog signals are connected (of any kind - wire, reg , etc ...). 
the trivial case is when there's a direct dependency (like A = ~B ) and very easy to trace. 
but take a look at the following pseudo code: here you can notice that D in indirectly influenced by A. although it's easy to trace it in this example, there can be very large code blocks, with many distinguished modules, each written in different file... what make it much more difficult to trace  



clk = A and ~B
always (clk rise) 
   if (X==0)    
      D = C;
   else 
      D = 0; 
end


thanks !!!


Originally posted in cdnusers.org by zcabeli11
Parents

  • If you only need to do a few you can use Verdi from Novas to do this. They can create a "cone" from a point. You can use this to trace backwards to a Flop or PI and stop. You would write out this Verilog and then search for the Signal you are interested in seeing if it is in the fan in cone. If you want to go back through flops I believe this is possible but I have never done that. I suggest you get with a Novas AE and explore this future.


    Originally posted in cdnusers.org by bryan
Reply

  • If you only need to do a few you can use Verdi from Novas to do this. They can create a "cone" from a point. You can use this to trace backwards to a Flop or PI and stop. You would write out this Verilog and then search for the Signal you are interested in seeing if it is in the fan in cone. If you want to go back through flops I believe this is possible but I have never done that. I suggest you get with a Novas AE and explore this future.


    Originally posted in cdnusers.org by bryan
Children
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