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non deterministic ff in verilog :

Hello, one of my FF's is implemented as follows : always @(posedge clk) data 1 / data 0 / prev_data 1 -> 0 i get different results on 2 run (after 1 cycle) one time 'data' remains 0, and on another run it rise from 0 to 1. i assume it caused since in the time of the clk rise, prev_data is falling, and therefore, 'data' doesn't succeed in sampling on time. is it possible that verilog is not deterministic in this case ? thanks,

Originally posted in cdnusers.org by zcabeli11

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archive over 17 years ago

hello ajeetha,

would it be ok of ii send you the wave results on email ?

thanks,

Originally posted in cdnusers.org by zcabeli11
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archive over 17 years ago

hello ajeetha,

would it be ok of ii send you the wave results on email ?

thanks,

Originally posted in cdnusers.org by zcabeli11
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