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Hi,

How can one effectively check for the FSM Transition Correctness using SV Assertions?

-Vivek C. Prasad


Originally posted in cdnusers.org by prasad_vc
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    I don't think we can really give a course in assertion-based verification in this forum. But ABV sounds exactly tailored for the kind of things you want to do. ABV allows you to take an english-language specification like "when 'ap' is asserted, 1 clock after 'an' is asserted, it will go to 0" and translate it into HDL that can be embedded in your test.

    an_once: assert property ( @(posedge clk) ( ap && an ) |=> ( !an ) );

    This will be ignored by the synthesis tools, so it can be put directly in your FSM code and travel with it. It serves as both a dynamic checker for correct behavior and as documentation of the protocol that the FSM was written to implement.

    I could go on, but this would become a marketing presentation pretty quickly, since I'm a believer in the efficacy of ABV.


    Originally posted in cdnusers.org by TAM
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  • archive

    I don't think we can really give a course in assertion-based verification in this forum. But ABV sounds exactly tailored for the kind of things you want to do. ABV allows you to take an english-language specification like "when 'ap' is asserted, 1 clock after 'an' is asserted, it will go to 0" and translate it into HDL that can be embedded in your test.

    an_once: assert property ( @(posedge clk) ( ap && an ) |=> ( !an ) );

    This will be ignored by the synthesis tools, so it can be put directly in your FSM code and travel with it. It serves as both a dynamic checker for correct behavior and as documentation of the protocol that the FSM was written to implement.

    I could go on, but this would become a marketing presentation pretty quickly, since I'm a believer in the efficacy of ABV.


    Originally posted in cdnusers.org by TAM
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