SV Monitor

Following is the Scenario,

event got_11;
event got_01;

always @(ap, an) begin
if (ap==1 && an == 1)
-> got_11;
else if (ap==0 && an ==1)
-> got_01;
end

// How can i use the sequence/property to implement this.
// 'e'-Language has {@got_11;@got_01} @aclk;
// Can i use something similar in SV???

I really don't know if I am interpreting your question correctly, but I'll make a try at it and you can elaborate some more if I am misinterpreting you.

The following coverage points can be used to see if you've visited a particular state in your design.

got_11: cover property ( @(posedge aclk) ap == 1 && an == 1 );
got_01: cover property ( @(posedge aclk) ap == 0 && an == 1 );

You could then use the functional coverage tool (icc) to tell if those particular coverage points were reached.

If you wanted to react to those coverage points in your testbench, you can add a action block to the coverage point.

got_11: cover property ( @(posedge aclk) ap == 1 && an == 1 )
begin
$display("Got 11!");
test11 = 1;
...
end

If you are simply looking for coverage of your FSM, then you don't really need to add SV code. The icc tool will extract the FSM and tell you the state and transition or arc coverage of your tests.

TAM,

Thanks for your feedback.
My objective is to check whether the I/O Lines are following the protocol properly. So, the monitor will snoop the lines to check that protocol is not violated.

In my example, i am emitting events when the ap/an lines have desired values, how can i use Assertions in SV for taking the events as input and monitor the state transitions?

And yes, i can use the above guidelines for coverage.

This is probably a better question for the ABV forum, but here is what I came up with: ; //event got_11, got_01; bit got_11, got_01; always @(ap, an) begin if (ap==1 && an == 1) begin //-> got_11; got_11 = 1; got_01 = 0; end else if (ap==0 && an ==1) begin //-> got_01; got_01 = 1; got_11 = 0; end end assert property (@(ap, an) $rose(got_11) |=> $rose(got_01)); endmodule module test(); bit ap, an; always #5 ap = ~ap; always @(ap) #3 an = ~an; monitor mon(.ap, .an); endmodule Tim

I don't think we can really give a course in assertion-based verification in this forum. But ABV sounds exactly tailored for the kind of things you want to do. ABV allows you to take an english-language specification like "when 'ap' is asserted, 1 clock after 'an' is asserted, it will go to 0" and translate it into HDL that can be embedded in your test.

an_once: assert property ( @(posedge clk) ( ap && an ) |=> ( !an ) );

This will be ignored by the synthesis tools, so it can be put directly in your FSM code and travel with it. It serves as both a dynamic checker for correct behavior and as documentation of the protocol that the FSM was written to implement.

I could go on, but this would become a marketing presentation pretty quickly, since I'm a believer in the efficacy of ABV.

If you are a Cadence customer, you can visit http://myipcm.cadence.com and access all of our methodology documentation for implementing ABV.

Tim