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Hi,

How can one effectively check for the FSM Transition Correctness using SV Assertions?

-Vivek C. Prasad


Originally posted in cdnusers.org by prasad_vc
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    Posted By prasad_vc on 4/03/2008 10:02 PM
    TAM,

    Thanks for your feedback.
    My objective is to check whether the I/O Lines are following the protocol properly. So, the monitor will snoop the lines to check that protocol is not violated.

    In my example, i am emitting events when the ap/an lines have desired values, how can i use Assertions in SV for taking the events as input and monitor the state transitions?

    And yes, i can use the above guidelines for coverage.

    It is simpler in SV(A) - no need of extra events! Use the booleans as in the if..else and write your SVA (as others have shown the code snippet). Other benefit is - this can be readily used by a formal checker like IFV.

    Regards
    Ajeetha, CVC
    www.noveldv.com


    Originally posted in cdnusers.org by ajeetha
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  • archive

    Posted By prasad_vc on 4/03/2008 10:02 PM
    TAM,

    Thanks for your feedback.
    My objective is to check whether the I/O Lines are following the protocol properly. So, the monitor will snoop the lines to check that protocol is not violated.

    In my example, i am emitting events when the ap/an lines have desired values, how can i use Assertions in SV for taking the events as input and monitor the state transitions?

    And yes, i can use the above guidelines for coverage.

    It is simpler in SV(A) - no need of extra events! Use the booleans as in the if..else and write your SVA (as others have shown the code snippet). Other benefit is - this can be readily used by a formal checker like IFV.

    Regards
    Ajeetha, CVC
    www.noveldv.com


    Originally posted in cdnusers.org by ajeetha
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