connecting interfaces to old fashion DUTs

While it looks clean (or so) how to connect two module exposing interfaces, My basic question is how to connect a system verilog interface to a old fashion verilog DUT
I have an issue connecting an interface to a DUTwhich is an old fashion verilog module (Verilog 1996), i.e. with traditional port declaration
The interface looks like this

interface xram_if

  (output CLK, nRST);

timeunit 1ns;
timeprecision 1ps;

  logic [7:0] AD;
  logic ALE;
  logic nWR;
  logic nRD;

  modport master (
    output nWR,
    output nRD,
    output ALE,
    inout AD,
    import write,
    import read
  );

  modport slave (
    input nWR,
    input nRD,

    input ALE,

  endtask // init

  task write (
    input t_xram_addr addr,
    input t_xram_data data
  );
  begin
   ....

  end

  endtask // write

  task read (
    input t_xram_addr addr,
    output t_xram_data data
  );
  begin
...

  end
 endtask

I want to instantiate it in a test bench, e.g.

  xram_if xramif (
    .CLK(MCLK),
    .nRST(nRST)
  );

and I need a master interface to drive my DUT (so there are modports
above)
My DUT does not support interfaces (it is Verilog 2001)
How do I specifiy
- which interface flavor (master or slave)
How doi I connect my interface to the DUT?

The following does not work ...

I think I am missing sopme big points here ...

  vdt_top i_vdt_top(
...
    .access_if_ale_i               (xramif.master.ALE),
    .access_if_nwr_i               (xramif.master.nWR),
    .access_if_nrd_i               (xramif.master.nRD),
...

    .access_if_ad_0                (xramif.master.AD[0]),
    .access_if_ad_1                (xramif.master.AD[1]),
    .access_if_ad_2                (xramif.master.AD[2]),
    .access_if_ad_3                (xramif.master.AD[3]),
    .access_if_ad_4                (xramif.master.AD[4]),
    .access_if_ad_5                (xramif.master.AD[5]),
    .access_if_ad_6                (xramif.master.AD[6]),
    .access_if_ad_7                (xramif.master.AD[7]),

...

);