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connecting interfaces to old fashion DUTs

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While it looks clean (or so) how to connect two module exposing interfaces, My basic question is how to connect a system verilog interface to a old fashion verilog DUT
I have an issue connecting an interface to a DUTwhich is an old fashion verilog module (Verilog 1996), i.e. with traditional port declaration
The interface looks like this

interface xram_if

  (output CLK, nRST);

timeunit 1ns;
timeprecision 1ps;

  logic [7:0] AD;
  logic ALE;
  logic nWR;
  logic nRD;

  modport master (
    output nWR,
    output nRD,
    output ALE,
    inout AD,
    import write,
    import read
  );

  modport slave (
    input nWR,
    input nRD,

    input ALE,

    inout AD
  );
....
  task init ();
   begin
    ALE = 0;
    nRD = 1;
    nWR = 1;
    AD = `DATAW'bz;
    nrst    = 1'b1;
...

  endtask // init

  task write (
    input t_xram_addr addr,
    input t_xram_data data
  );
  begin
   ....

  end

  endtask // write

  task read (
    input t_xram_addr addr,
    output t_xram_data data
  );
  begin
...

  end
 endtask

I want to instantiate it in a test bench, e.g.

  xram_if xramif (
    .CLK(MCLK),
    .nRST(nRST)
  );

and I need a master interface to drive my DUT (so there are modports
above)
My DUT does not support interfaces (it is Verilog 2001)
How do I specifiy
- which interface flavor (master or slave)
How doi I connect my interface to the DUT?

The following does not work ...

I think I am missing sopme big points here ...

  vdt_top i_vdt_top(
...
    .access_if_ale_i               (xramif.master.ALE),
    .access_if_nwr_i               (xramif.master.nWR),
    .access_if_nrd_i               (xramif.master.nRD),
...

    .access_if_ad_0                (xramif.master.AD[0]),
    .access_if_ad_1                (xramif.master.AD[1]),
    .access_if_ad_2                (xramif.master.AD[2]),
    .access_if_ad_3                (xramif.master.AD[3]),
    .access_if_ad_4                (xramif.master.AD[4]),
    .access_if_ad_5                (xramif.master.AD[5]),
    .access_if_ad_6                (xramif.master.AD[6]),
    .access_if_ad_7                (xramif.master.AD[7]),

...

);


I feel I am missing some big points here ...

thanks to whoever will help on this



Originally posted in cdnusers.org by marco.stanzani
Parents

  • Hello tplyant
    thanks for looking into my issue, first.
    Then, assuming modport is not there any longer, i.e

    interface xram_if

      (
        output CLK,
        output nRST
     
      );

    timeunit 1ns;
    timeprecision 1ps;

     
      logic [`DATAW-1:0] AD;
      logic ALE;
      logic nWR;
      logic nRD;

      task write (
        input t_xram_addr addr,
        input t_xram_data data
      );
      begin
       nWR=1;
       nRD=1;
       AD = `DATAW'bz;

       ALE=1;
       #(tLHLL-tAVLL);
       AD = addr[`DATAW-1:0];
       #(tAVLL);  // Addrss valid to ALE low
       ALE=0;
       #(tLLAX);
       AD =`DATAW'bz;
       #(tLLWL-tLLAX-tQVWX);
      .....
     etc

    I tried to connect interface signals, which I did not declared as ports, just 'logic' in the inetrface

    ....
        .access_if_ale_i               (xramif.ALE),                   
        .access_if_nwr_i               (xramif.nWR),                   
        .access_if_nrd_i               (xramif.nRD),                   
    ....

        .access_if_ad_0                (xramif.AD[0]),            <<-- inout         
        .access_if_ad_1                (xramif.AD[1]),                     

    ALE, nWR,nRD seems OK, but I havve an issu with bidirs

        .access_if_ad_0                (xramif.AD[0]),
                                                |
    ncelab: *E,CUVMIO (../hdl/tb.v,213|44): port connections to inout ports must be collapsible, that is, they must be nets.
    Defininmg AD ad tri instead of logic does not help ...

    regards

     



    Originally posted in cdnusers.org by marco.stanzani
Reply

  • Hello tplyant
    thanks for looking into my issue, first.
    Then, assuming modport is not there any longer, i.e

    interface xram_if

      (
        output CLK,
        output nRST
     
      );

    timeunit 1ns;
    timeprecision 1ps;

     
      logic [`DATAW-1:0] AD;
      logic ALE;
      logic nWR;
      logic nRD;

      task write (
        input t_xram_addr addr,
        input t_xram_data data
      );
      begin
       nWR=1;
       nRD=1;
       AD = `DATAW'bz;

       ALE=1;
       #(tLHLL-tAVLL);
       AD = addr[`DATAW-1:0];
       #(tAVLL);  // Addrss valid to ALE low
       ALE=0;
       #(tLLAX);
       AD =`DATAW'bz;
       #(tLLWL-tLLAX-tQVWX);
      .....
     etc

    I tried to connect interface signals, which I did not declared as ports, just 'logic' in the inetrface

    ....
        .access_if_ale_i               (xramif.ALE),                   
        .access_if_nwr_i               (xramif.nWR),                   
        .access_if_nrd_i               (xramif.nRD),                   
    ....

        .access_if_ad_0                (xramif.AD[0]),            <<-- inout         
        .access_if_ad_1                (xramif.AD[1]),                     

    ALE, nWR,nRD seems OK, but I havve an issu with bidirs

        .access_if_ad_0                (xramif.AD[0]),
                                                |
    ncelab: *E,CUVMIO (../hdl/tb.v,213|44): port connections to inout ports must be collapsible, that is, they must be nets.
    Defininmg AD ad tri instead of logic does not help ...

    regards

     



    Originally posted in cdnusers.org by marco.stanzani
Children
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