overriding the module parameters

Hi everyone,
I have created a test bench which has some parameters and it instantiate a module which also has some parameters on its on. i pass the test bench's parameters to the parameters of the instance of the module and it works fine however when i try to override the test bench's parameter during the simulationg, it gives the following error:
Error: (vsim-3852) Invalid override of parameter
i do the following to simulate
vsim -GWIDTH=16 -GADDR_BITSD=9 tb

(WIDTH and ADDR_BITS are parameters of test bench which are passed to parameters of an instance of a module within the test case)
this is how i defined my test bench parameter
module tb #(parameter WIDTH=16,parameter ADDR_BITS=9);
this is how i instantiated the module within the testbench
generator#(WIDTH,ADDR_BITS) g1 (.*);

could someone tell me what could i do during the simulation to override parameters of the test bench ?