binding of simple inout ports to hdl wire (specman 6.2)

Hi,
 
   I am trying to bind simple inout ports to hdl wires. Specman tool is giving the following error. (specman tool version 6.2)

           *** Error: Bound sets cannot have an external inout port with other
        external ports.
         sys.simple_evc.smp.sig_DBus: NCVLOG inout simple_port of uint (bits: 32)
                 Also externally connected to agent 'NCVLOG',
                 using hdl_path() 'DBus'

    The following is the sample code used for binding the simple port  

     sig_DBus : simple_port of uint(bits:32) is instance;
       keep soft sig_DBus.hdl_path() == "DBus";
       keep sig_DBus.declared_range() == "[31:0]";
       keep sig_DBus.verilog_wire() == TRUE;
       keep bind(sig_DBus, external);

    What could be the reason for this error?  and how to get around from this problem?  

Thanks & Regards,
Arjun.