Stats

  • Locked Locked
  • Replies 3
  • Subscribers 64
  • Views 14313
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Clock Generation using sys.any

archive

Hi Everybody,

I am stuck in a doubt that seems to be a really easy one for expert users, but that is my first VE .

Problem: My DUT needs a clock which I don't want to create in HDL, I would like to generate it in Specman.

My First Approach: I was reading the Verification Advisor which recommends in this case the use of sys.any. But in the same Verification Advisor is written:

sys.any is a pre-defined event that has two main functions:
* Without a simulator
sys.any acts like a clock that ticks every cycle (the highest possible frequency) and can be used to sample other clocks, events, and TCMs.
* With a simulator
sys.any is emitted on every callback of the simulator (thus being unpredictable) and should not be used as a clock unless there is no other option.

Questions:
1 - As long as I want to use this generated clock to test the DUT how would I do? The Advisor says that sys.any is unpredictable when acting with simulator..
2 - How would I know what is the frequency which I am generating the clock? How would I determine the highest possible frequency?
3 - Is there any other way for doing that or should I give up and use verilog?

Any help would be really appreciated!
Thanks,
Filipe Tabarani

Ps: I am currently verifying a I2C implementation, if someone has any document, eVC or tips which could helps. I would be really thanks.  

 


Originally posted in cdnusers.org by tabarani
Parents

  • Sorry for the garbled reply earlier.

    Script started on Thu 13 Mar 2008 05:35:46 PM CDT
    id: cannot find name for group ID 1001
    ca[jigar@lnx-jigar clock_gen]$ cat clock_gen.e
    <'

    unit clock_driver {
      clk: inout simple_port of bit is instance;
      keep bind (clk, external);
      keep soft clk.hdl_path() == "clock";

      gen_clock() @sys.any is {
         clk$ = 0;
         while TRUE {
           -- Create clock with 200 ns period, 50% duty cycle
           wait delay(100 ns);
           clk$ = ~clk$;
         };
      };

      run() is also {
        start gen_clock();
      };
    };

    extend sys {
        clock_driver_i: clock_driver is instance;
        keep clock_driver_i.hdl_path() == "~/top";
    };


    '>
    [jigar@lnx-jigar clock_gen]$ cat top.v
    module top();
      reg clock;

      initial begin
        @(posedge clock);
        $display("Got postive edge of clock at time %0d", $time);
        @(negedge clock);
        $display("Got negative edge of clock at time %0d", $time);
        $finish;
      end
    endmodule
    [jigar@lnx-jigar clock_gen]$ cat [K[K[Kirun -nosncomp co[Klock_gen.e top.v
    irun: 06.20-s004: (c) Copyright 1995-2008 Cadence Design Systems, Inc.
    Loading snapshot worklib.top:v .................... Done
    Initializing Incisive Enterprise Simulator (06.20)  -  Linked on Sun Jan 13
    16:31:20 2008

    Protected by U.S. Patents 6,920,583; 6,918,076; 6,907,599; 6,687,662;
    6,684,359; 6,675,138; 6,530,054; 6,519,727; 6,502,232; 6,499,132; 6,487,704;
    6,347,388; 6,219,809; 6,182,258; 6,141,630; Other Patents Pending.

    exit
    Checking license ... OK
    Doing setup ...
    Generating the test using seed 1...

    Starting the test ...
    Running the test ...
    Running should now be initiated from the simulator side
    ncsim> source /localhome/jigar/softwares/ies62/IUS62/tools/inca/files/ncsimrc
    ncsim> run
    Got postive edge of clock at time 100
    Got negative edge of clock at time 200
    nc_specman is doing end-of-test operations
    Checking the test ...
    Checking is complete - 0 DUT errors, 0 DUT warnings.
    End-of-test operations are completed
    Simulation complete via $finish(1) at time 200 NS + 1
    ./top.v:9     $finish;
    ncsim> exit

    Script done on Thu 13 Mar 2008 05:36:13 PM CDT





    Originally posted in cdnusers.org by pjigar
Reply

  • Sorry for the garbled reply earlier.

    Script started on Thu 13 Mar 2008 05:35:46 PM CDT
    id: cannot find name for group ID 1001
    ca[jigar@lnx-jigar clock_gen]$ cat clock_gen.e
    <'

    unit clock_driver {
      clk: inout simple_port of bit is instance;
      keep bind (clk, external);
      keep soft clk.hdl_path() == "clock";

      gen_clock() @sys.any is {
         clk$ = 0;
         while TRUE {
           -- Create clock with 200 ns period, 50% duty cycle
           wait delay(100 ns);
           clk$ = ~clk$;
         };
      };

      run() is also {
        start gen_clock();
      };
    };

    extend sys {
        clock_driver_i: clock_driver is instance;
        keep clock_driver_i.hdl_path() == "~/top";
    };


    '>
    [jigar@lnx-jigar clock_gen]$ cat top.v
    module top();
      reg clock;

      initial begin
        @(posedge clock);
        $display("Got postive edge of clock at time %0d", $time);
        @(negedge clock);
        $display("Got negative edge of clock at time %0d", $time);
        $finish;
      end
    endmodule
    [jigar@lnx-jigar clock_gen]$ cat [K[K[Kirun -nosncomp co[Klock_gen.e top.v
    irun: 06.20-s004: (c) Copyright 1995-2008 Cadence Design Systems, Inc.
    Loading snapshot worklib.top:v .................... Done
    Initializing Incisive Enterprise Simulator (06.20)  -  Linked on Sun Jan 13
    16:31:20 2008

    Protected by U.S. Patents 6,920,583; 6,918,076; 6,907,599; 6,687,662;
    6,684,359; 6,675,138; 6,530,054; 6,519,727; 6,502,232; 6,499,132; 6,487,704;
    6,347,388; 6,219,809; 6,182,258; 6,141,630; Other Patents Pending.

    exit
    Checking license ... OK
    Doing setup ...
    Generating the test using seed 1...

    Starting the test ...
    Running the test ...
    Running should now be initiated from the simulator side
    ncsim> source /localhome/jigar/softwares/ies62/IUS62/tools/inca/files/ncsimrc
    ncsim> run
    Got postive edge of clock at time 100
    Got negative edge of clock at time 200
    nc_specman is doing end-of-test operations
    Checking the test ...
    Checking is complete - 0 DUT errors, 0 DUT warnings.
    End-of-test operations are completed
    Simulation complete via $finish(1) at time 200 NS + 1
    ./top.v:9     $finish;
    ncsim> exit

    Script done on Thu 13 Mar 2008 05:36:13 PM CDT





    Originally posted in cdnusers.org by pjigar
Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.