Clock Generation using sys.any

Hi Everybody,

I am stuck in a doubt that seems to be a really easy one for expert users, but that is my first VE .

Problem: My DUT needs a clock which I don't want to create in HDL, I would like to generate it in Specman.

My First Approach: I was reading the Verification Advisor which recommends in this case the use of sys.any. But in the same Verification Advisor is written:

sys.any is a pre-defined event that has two main functions:
* Without a simulator
sys.any acts like a clock that ticks every cycle (the highest possible frequency) and can be used to sample other clocks, events, and TCMs.
* With a simulator
sys.any is emitted on every callback of the simulator (thus being unpredictable) and should not be used as a clock unless there is no other option.

Questions:
1 - As long as I want to use this generated clock to test the DUT how would I do? The Advisor says that sys.any is unpredictable when acting with simulator..
2 - How would I know what is the frequency which I am generating the clock? How would I determine the highest possible frequency?
3 - Is there any other way for doing that or should I give up and use verilog?

Any help would be really appreciated!
Thanks,
Filipe Tabarani

Ps: I am currently verifying a I2C implementation, if someone has any document, eVC or tips which could helps. I would be really thanks.