• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Functional Verification
CDNS - double leaderboard script

Functional Verification

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Latest Posts

  • Create a new Post
  • Discussion

    Bidirectional has() and count() List Pseudo-Methods

    Category: Functional Verification

    By IonutC

    $usertype

    •

    updated over 12 years ago by IonutC

    2 replies • 14996 views
  • Discussion

    Engineering Fix

    Category: Functional Verification

    By Avni

    $usertype

    •

    updated over 12 years ago by Avni

    2 replies • 14520 views
  • Discussion

    SVA library in Cadence INCISIV

    Category: Functional Verification

    By Maisum

    $usertype

    •

    updated over 12 years ago by StephenH

    2 replies • 15730 views
  • Discussion

    re : parameterized sequences & property blocks in simvision

    Category: Functional Verification

    By Srikanth Madam

    $usertype

    •

    updated over 12 years ago by Srikanth Madam

    2 replies • 2142 views
  • Discussion

    Failure of liveness property

    Category: Functional Verification

    By Wesh

    $usertype

    •

    updated over 12 years ago by TAM1

    2 replies • 15039 views
  • Discussion

    Is it possible to make a system verilog module from the library manager GUI?

    Category: Functional Verification

    By giorgiaz

    $usertype

    •

    started over 12 years ago

    0 replies • 13976 views
  • Discussion

    Why do I get an error when I try to generate (any) system Verilog module?

    Category: Functional Verification

    By giorgiaz

    $usertype

    •

    started over 12 years ago

    0 replies • 14633 views
  • Discussion

    VCS to IRUN Conversion Error, UVM-1.1 System Verilog

    Category: Functional Verification

    By Maisum

    $usertype

    •

    updated over 12 years ago by Maisum

    2 replies • 16253 views
  • Discussion

    IMC Exclusion Problem

    Category: Functional Verification

    By Enginerd

    $usertype

    •

    updated over 12 years ago by StephenH

    1 replies • 17806 views
  • Discussion

    SystemC module array of ports binding with Verilog module

    Category: Functional Verification

    By archive

    $usertype

    •

    started over 13 years ago

    0 replies • 14790 views
  • Discussion

    UVM_REG:: How can we use multiple bfm drivers to same regmap using uvm registers

    Category: Functional Verification

    By Santosh504

    $usertype

    •

    started over 13 years ago

    0 replies • 14085 views
  • Discussion

    How to read the Stream Counts in irun 10.2 profiler

    Category: Functional Verification

    By tktk

    $usertype

    •

    updated over 13 years ago by tktk

    4 replies • 16482 views
  • Discussion

    Additional TCL Documentation?

    Category: Functional Verification

    By neffk

    $usertype

    •

    started over 13 years ago

    0 replies • 13791 views
  • Discussion

    Reg:Coverage improvement

    Category: Functional Verification

    By Mohan P

    $usertype

    •

    started over 13 years ago

    0 replies • 513 views
  • Discussion

    Need help in assertion based connectivity checking

    Category: Functional Verification

    By SnehalC

    $usertype

    •

    updated over 13 years ago by SnehalC

    7 replies • 17890 views
<>

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2026 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information