Functional Verification

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Discussion

TCL based assertion for connectivity check

Category: Functional Verification

By harsharaj
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updated over 13 years ago by harsharaj

5 replies • 18592 views
Discussion

UVM_REG backdoor access

Category: Functional Verification

By sega
•
started over 13 years ago

0 replies • 16897 views
Discussion

Issue in merging two coverage runs with different checksums in IMC.

Category: Functional Verification

By Clair
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started over 13 years ago

0 replies • 16646 views
Discussion

Retrieve Flat Net Wire Properties using TCL

Category: Functional Verification

By dk631
•
updated over 13 years ago by oldmouldy

1 replies • 16066 views
Discussion

Bidirectional has() and count() List Pseudo-Methods

Category: Functional Verification

By IonutC
•
updated over 13 years ago by IonutC

2 replies • 15967 views
Discussion

Engineering Fix

Category: Functional Verification

By Avni
•
updated over 13 years ago by Avni

2 replies • 15363 views
Discussion

SVA library in Cadence INCISIV

Category: Functional Verification

By Maisum
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updated over 13 years ago by StephenH

2 replies • 16653 views
Discussion

re : parameterized sequences & property blocks in simvision

Category: Functional Verification

By Srikanth Madam
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updated over 13 years ago by Srikanth Madam

2 replies • 2508 views
Discussion

Failure of liveness property

Category: Functional Verification

By Wesh
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updated over 13 years ago by TAM1

2 replies • 16167 views
Discussion

Is it possible to make a system verilog module from the library manager GUI?

Category: Functional Verification

By giorgiaz
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started over 13 years ago

0 replies • 14691 views
Discussion

Why do I get an error when I try to generate (any) system Verilog module?

Category: Functional Verification

By giorgiaz
•
started over 13 years ago

0 replies • 15365 views
Discussion

VCS to IRUN Conversion Error, UVM-1.1 System Verilog

Category: Functional Verification

By Maisum
•
updated over 13 years ago by Maisum

2 replies • 17247 views
Discussion

IMC Exclusion Problem

Category: Functional Verification

By Enginerd
•
updated over 13 years ago by StephenH

1 replies • 18950 views
Discussion

SystemC module array of ports binding with Verilog module

Category: Functional Verification

By archive
•
started over 13 years ago

0 replies • 15601 views
Discussion

UVM_REG:: How can we use multiple bfm drivers to same regmap using uvm registers

Category: Functional Verification

By Santosh504
•
started over 13 years ago

0 replies • 14826 views

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