Functional Verification

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Discussion

Is it possible to make a system verilog module from the library manager GUI?

Category: Functional Verification

By giorgiaz

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started over 12 years ago

0 replies • 13606 views
Discussion

Why do I get an error when I try to generate (any) system Verilog module?

Category: Functional Verification

By giorgiaz

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started over 12 years ago

0 replies • 14242 views
Discussion

VCS to IRUN Conversion Error, UVM-1.1 System Verilog

Category: Functional Verification

By Maisum

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updated over 12 years ago by Maisum

2 replies • 15822 views
Discussion

IMC Exclusion Problem

Category: Functional Verification

By Enginerd

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updated over 12 years ago by StephenH

1 replies • 17290 views
Discussion

SystemC module array of ports binding with Verilog module

Category: Functional Verification

By archive

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started over 12 years ago

0 replies • 14371 views
Discussion

UVM_REG:: How can we use multiple bfm drivers to same regmap using uvm registers

Category: Functional Verification

By Santosh504

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started over 12 years ago

0 replies • 13710 views
Discussion

How to read the Stream Counts in irun 10.2 profiler

Category: Functional Verification

By tktk

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updated over 12 years ago by tktk

4 replies • 15963 views
Discussion

Additional TCL Documentation?

Category: Functional Verification

By neffk

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started over 12 years ago

0 replies • 13407 views
Discussion

Reg:Coverage improvement

Category: Functional Verification

By Mohan P

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started over 12 years ago

0 replies • 487 views
Discussion

Need help in assertion based connectivity checking

Category: Functional Verification

By SnehalC

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updated over 12 years ago by SnehalC

7 replies • 17326 views
Discussion

IFV assertion check problem

Category: Functional Verification

By stone14041

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updated over 12 years ago by JoergM

1 replies • 13583 views
Discussion

Tracking regression results with an SQLITE database

Category: Functional Verification

By andymont

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updated over 12 years ago by StephenH

4 replies • 15992 views
Discussion

How to overcome DC convergence error in ultrasim?

Category: Functional Verification

By bsddsb

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updated over 12 years ago by glennramalho

1 replies • 13905 views
Discussion

Re: Simulating an already generated snap-shot.

Category: Functional Verification

By tpylant

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started over 12 years ago

0 replies • 13175 views
Discussion

irun: Simulating an already generated snap-shot.

Category: Functional Verification

By Abid

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updated over 12 years ago by Abid

4 replies • 16646 views

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