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In encounter RTL compiler, how can I apply speed or size optimization options

learnlearn1

 In Synopsys,  HDL files can be synthesized with speed or size optimization options. 

How can do the same thing in the rc RTL compiler when I synthesize a file?

Thanks!

  • grasshopper

    Hi learnlearn1,

    this is not much different from DC. RC uses SDC constraints for timing requirements in the same way DC does. You could certainly use RC native constraints but using SDC will allow you to use the same constraints in for all tools without having to convert them. As per area constraints, is there any reason why you would want your design to be bigger. RC always tries to reach the smallest possible design. In the DC world a lot of people set the area goal to 0 which only causes the tool to unncessarily thrash and leads to worse runtime. RC certainly has optimization switches that may lead to better area, etc. but generally speaking, the design output should be the smallest possible design provided the timing constraints are met. Last but not least RC can use CPF constraints for power requirements as well as yield coefficient tables if you want to enable yield optimization.

     hope this helps,

    gh-

  • learnlearn1
    Dear gh,
    Thanks for your reply. Your info is helpful to me.
    thanks!
    learnlearn1

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