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Specifying timing path for synchronous circuits

gchalive

 Hi..

 How do I specify a timing path of a synchronous circuit in Cadence RTL Compielr. What I want is to synthesize the circuit considering the path I specified as the critical path. 

Suppose I have two seqential elements and a combinational logic in between that generates the clock of the second flip flop, I want my critical path delay to be (clk_q)FF1+Comb_delay+(clk_q)FF2. Is there a command in RC that does this.

 

Thanks

 

Parents

  •  Hi gchalive,

     if you have an exact delay requirement, usually logic synthesis tools are not best suited for such task. In those cases designers frequently specify that logic by hand and preserve it or create a macro for it. The challenge is that, even if properly constrained, there are just too many unknowns. For example, if the synthesis tools implemented a circuit to have a delay of 1.35 ns and it turned out that the logic was scattered over a giant die, then the timing would not be what the designer expected and likely would be larger. Normally flow would be to constraint your clocks and let the tool optimize to the best area, timing, power, and yield. If you have a generated, you would simply use the related SDC commands to define its characteristics such that RC can optimize the logic it drive accordingly. Some of the commands you would use are commands like

    create_generated_clock

    set_clock_latency

    set_clock_uncertainty

    hope this helps,

    gh-

Reply

  •  Hi gchalive,

     if you have an exact delay requirement, usually logic synthesis tools are not best suited for such task. In those cases designers frequently specify that logic by hand and preserve it or create a macro for it. The challenge is that, even if properly constrained, there are just too many unknowns. For example, if the synthesis tools implemented a circuit to have a delay of 1.35 ns and it turned out that the logic was scattered over a giant die, then the timing would not be what the designer expected and likely would be larger. Normally flow would be to constraint your clocks and let the tool optimize to the best area, timing, power, and yield. If you have a generated, you would simply use the related SDC commands to define its characteristics such that RC can optimize the logic it drive accordingly. Some of the commands you would use are commands like

    create_generated_clock

    set_clock_latency

    set_clock_uncertainty

    hope this helps,

    gh-

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