Specifying timing path for synchronous circuits

 Hi gchalive,

 if you have an exact delay requirement, usually logic synthesis tools are not best suited for such task. In those cases designers frequently specify that logic by hand and preserve it or create a macro for it. The challenge is that, even if properly constrained, there are just too many unknowns. For example, if the synthesis tools implemented a circuit to have a delay of 1.35 ns and it turned out that the logic was scattered over a giant die, then the timing would not be what the designer expected and likely would be larger. Normally flow would be to constraint your clocks and let the tool optimize to the best area, timing, power, and yield. If you have a generated, you would simply use the related SDC commands to define its characteristics such that RC can optimize the logic it drive accordingly. Some of the commands you would use are commands like

create_generated_clock

set_clock_latency

set_clock_uncertainty

hope this helps,

gh-

Hey, you reply answered my question well. Let me be clear with my understanding.

A synthesizer can take the following timing paths as valid:

1)input to register (Data to Q)

2)register to register(clk of reg1 to ip of reg2)

3)register to ouptut (clk of reg to Q)

4)input to output (in asynchronous circuits)

In my case the path I specified (reg to regclk+regclk to out)does not fall into any of those mentioned. So there is no way a synthesizer can take it as a valid timing path??

Please correct me if I am missing anything.

 Thanks

 I guess we will now have to compound your understanding of my comment with my understanding of yours :)

Your understanding seems correct. However, I can think of some caveats to your comments:

In (4) it does not necessarily imply async circuits since input and output can have a clock reference and, in fact, it could even be the same reference. 

In the case of your question you have to be careful when you say the synthesis tool will not see the path as valid since there are a variety of circuit that synthesis tools will see as combinational clouds (pulse generators, clock doublers, etc.) and will analyze & optimize. What the tools will not do is infer how such clouds would modify the behavior of the clock. For example, a clock doubling circuit would not automatically end up with a clock of double the frequency on the output. Instead, the synthesis tool would propagate the original clock waveform on all loads. Also bear in mind that for STA, tools do not allow combinational timing loops (since they would analyze forever) so the tools will break the timing loop for analysis purposes only.

gh-

 Ya I understand your point. 

I have a structural netlist and I dont want to optimize the circuit for area. The only reason why I am synthesizing it is to find the the critical path delay to select a suitable clock period. If the synthesizer partitions the path for analysis, could I just add the path delay until I build the complete path and set up my clock period as that delay??

If you are not optimizing or infering any logic and you are using a structural netlist, wouldn't it make more sense to use an STA signoff tool like Encounter Timing System ?

 gh-

Yes actually I am looking to jump to PT or ETS...Thanks for ur help, I actually learnt so many things :)