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Specifying timing path for synchronous circuits

gchalive

 Hi..

 How do I specify a timing path of a synchronous circuit in Cadence RTL Compielr. What I want is to synthesize the circuit considering the path I specified as the critical path. 

Suppose I have two seqential elements and a combinational logic in between that generates the clock of the second flip flop, I want my critical path delay to be (clk_q)FF1+Comb_delay+(clk_q)FF2. Is there a command in RC that does this.

 

Thanks

 

Parents

  •  I guess we will now have to compound your understanding of my comment with my understanding of yours :)

    Your understanding seems correct. However, I can think of some caveats to your comments:

    In (4) it does not necessarily imply async circuits since input and output can have a clock reference and, in fact, it could even be the same reference. 

    In the case of your question you have to be careful when you say the synthesis tool will not see the path as valid since there are a variety of circuit that synthesis tools will see as combinational clouds (pulse generators, clock doublers, etc.) and will analyze & optimize. What the tools will not do is infer how such clouds would modify the behavior of the clock. For example, a clock doubling circuit would not automatically end up with a clock of double the frequency on the output. Instead, the synthesis tool would propagate the original clock waveform on all loads. Also bear in mind that for STA, tools do not allow combinational timing loops (since they would analyze forever) so the tools will break the timing loop for analysis purposes only.

    gh-

Reply

  •  I guess we will now have to compound your understanding of my comment with my understanding of yours :)

    Your understanding seems correct. However, I can think of some caveats to your comments:

    In (4) it does not necessarily imply async circuits since input and output can have a clock reference and, in fact, it could even be the same reference. 

    In the case of your question you have to be careful when you say the synthesis tool will not see the path as valid since there are a variety of circuit that synthesis tools will see as combinational clouds (pulse generators, clock doublers, etc.) and will analyze & optimize. What the tools will not do is infer how such clouds would modify the behavior of the clock. For example, a clock doubling circuit would not automatically end up with a clock of double the frequency on the output. Instead, the synthesis tool would propagate the original clock waveform on all loads. Also bear in mind that for STA, tools do not allow combinational timing loops (since they would analyze forever) so the tools will break the timing loop for analysis purposes only.

    gh-

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