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Specifying timing path for synchronous circuits

gchalive

 Hi..

 How do I specify a timing path of a synchronous circuit in Cadence RTL Compielr. What I want is to synthesize the circuit considering the path I specified as the critical path. 

Suppose I have two seqential elements and a combinational logic in between that generates the clock of the second flip flop, I want my critical path delay to be (clk_q)FF1+Comb_delay+(clk_q)FF2. Is there a command in RC that does this.

 

Thanks

 

Parents

  • Hey, you reply answered my question well. Let me be clear with my understanding.

    A synthesizer can take the following timing paths as valid:

    1)input to register (Data to Q)

    2)register to register(clk of reg1 to ip of reg2)

    3)register to ouptut (clk of reg to Q)

    4)input to output (in asynchronous circuits)

    In my case the path I specified (reg to regclk+regclk to out)does not fall into any of those mentioned. So there is no way a synthesizer can take it as a valid timing path??

    Please correct me if I am missing anything.

     Thanks

     

     

Reply

  • Hey, you reply answered my question well. Let me be clear with my understanding.

    A synthesizer can take the following timing paths as valid:

    1)input to register (Data to Q)

    2)register to register(clk of reg1 to ip of reg2)

    3)register to ouptut (clk of reg to Q)

    4)input to output (in asynchronous circuits)

    In my case the path I specified (reg to regclk+regclk to out)does not fall into any of those mentioned. So there is no way a synthesizer can take it as a valid timing path??

    Please correct me if I am missing anything.

     Thanks

     

     

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