STA in RC

 Hi gchalive,

 Synthesis without STA is like a car without a steering wheel. Competitive RTL synthesis tools need to be able to enfore not just the functionality but also the timing requirements as well as possibly power, area, and yield requirements.

In RC you can use the command

report timing...

 with all its options to see the timing of your circuit. Constraints can be entered using SDC format or native RC format. In general, SDC is recommended since that is compatible across a number of different tools and vendors whereas RC native is specific to RC. That being said, you can always enter in RC native and use the command

 write_sdc

 hope this helps,

gh-

 Hey,

 Thanks for your reply. Why I get to ask that question is that I clearly see a hold time violation in my circuit (based on the hand calculations) but when i report timing I dont see any violations. How do i report all timing violations in RC.

Thanks

RC does not perform any hold analysis or fixing. Doing this in a world that is wire-delay dominated is pretty futile since tools could end up inserting a large number of buffers for a problem that is non-existant once the real routing delay is inserted. Hold fixing is best left to Place & Route tools.

gh-