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STA in RC

gchalive

Hey,

 

Can RC perform the static timing analysis. How do I report set up and hold time violations in RC. 

 

Thanks

 

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  •  Hi gchalive,

     Synthesis without STA is like a car without a steering wheel. Competitive RTL synthesis tools need to be able to enfore not just the functionality but also the timing requirements as well as possibly power, area, and yield requirements.

    In RC you can use the command

    report timing...

     with all its options to see the timing of your circuit. Constraints can be entered using SDC format or native RC format. In general, SDC is recommended since that is compatible across a number of different tools and vendors whereas RC native is specific to RC. That being said, you can always enter in RC native and use the command

     write_sdc

     hope this helps,

    gh-

Reply

  •  Hi gchalive,

     Synthesis without STA is like a car without a steering wheel. Competitive RTL synthesis tools need to be able to enfore not just the functionality but also the timing requirements as well as possibly power, area, and yield requirements.

    In RC you can use the command

    report timing...

     with all its options to see the timing of your circuit. Constraints can be entered using SDC format or native RC format. In general, SDC is recommended since that is compatible across a number of different tools and vendors whereas RC native is specific to RC. That being said, you can always enter in RC native and use the command

     write_sdc

     hope this helps,

    gh-

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