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Synthesize problem

Hava

Hi there, I'm trying to synthesize my degin with CadenceRC. I have a makefile and a tcl scirpt to make the synthesization. At first it works, then I must did something wrong I cannot synthesize any more. It showed messages like this:

 

make: Circular my_design.vhd <- my_design.vhd dependency dropped

make: nothing to be donefor 'syn'

make: no rule to make the target . stop.

 

I cannot findout where is wrong.Could someone help me out of here?Thank you.

Tool: Cadence Encounter RC v08.10

Design: VHDL

Attachment: design source code, makefile, syn.tcl

Parents

  • Hi Hava,

    as the message indicates

    make: Circular my_design.vhd <- my_design.vhd dependency dropped

    make: nothing to be donefor 'syn'

    make: no rule to make the target . stop.

    The problem has nothing to do with RC but seems like your makefile has a circular dependancy. I suggest you review your makefile or share it with the community

    hope this helps,

    gh-

     

Reply

  • Hi Hava,

    as the message indicates

    make: Circular my_design.vhd <- my_design.vhd dependency dropped

    make: nothing to be donefor 'syn'

    make: no rule to make the target . stop.

    The problem has nothing to do with RC but seems like your makefile has a circular dependancy. I suggest you review your makefile or share it with the community

    hope this helps,

    gh-

     

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