Hi there, I'm trying to synthesize my degin with CadenceRC. I have a makefile and a tcl scirpt to make the synthesization. At first it works, then I must did something wrong I cannot synthesize any more. It showed messages like this:
make: Circular my_design.vhd <- my_design.vhd dependency dropped
make: nothing to be donefor 'syn'
make: no rule to make the target . stop.
I cannot findout where is wrong.Could someone help me out of here?Thank you.
Tool: Cadence Encounter RC v08.10
Attachment: design source code, makefile, syn.tcl
as the message indicates
The problem has nothing to do with RC but seems like your makefile has a circular dependancy. I suggest you review your makefile or share it with the community
hope this helps,
I am having the same problem and it was such annoying not knowing what to do, hope someone could help..thanks
You have really mentioned very good and useful things in your post and I am glad to be the part of it.