naming style for generate statement in RTL

 I have a generate statement in my verilog RTL.

 generate
        for(g=0; g<num_reg; g=g+1) begin

            wb_reg #(._address(reg_addr[g*_width+:_width]), ._default(reg_default[g*_width+:_width]),
                    ._bit_mask(reg_bit_mask[g*_width+:_width]), ._autoclr(reg_autoclr[g*_width+:_width])) wb_regs (
                .CLK_I(CLK_I),
                .RST_N_I(RST_N_I),
                .TEST_EN_I(TEST_EN_I),
                .ADR_I(SADR_I),
                .DAT_I(SDAT_I),
                .DAT_O(dat_o[g]),
                .ACK_O(ack_o[g]),
                .CYC_I(SCYC_I),
                .STB_I(SSTB_I),
                .WE_I(SWE_I),
                .REG_SEL_O(reg_sel_o[g]),
                .REG_DATA_O(reg_data_o[g]),
                .REG_DATA_I(ro_data[g*_width+:_width]),
                .REG_UPDATE_I(reg_update_i[g]));
        end
    endgenerate

After synthesizing with RC 8.1, the netlist generated for this block has following naming style.

 wb_reg__address8h03__default8h08__bit_mask8h8f__autoclr8hff\genblk1[0].wb_regs

Same naming sytle is in SDF file generated for this design using write_sdf  -design foo -version "OVI 3.0" -delimiter "/" > ${_OUTPUTS_PATH}/${DESIGN}_netlist.sdf . 

The problem is "." before wb_regs is causing syntax issue when running simulation using SDF file. The error is

 ncsdfc: *E,SDFIRE: "../../../synthesis/foo/outputs/foo_netlist.sdf", line 50115: Syntax error ".".
ncelab: *W,SDFCNC: Cannot compile SDF file, ../../../synthesis/foo/outputs/foo_netlist.sdf - skipping annotation.

I have tried 

 set_attribute hdl_array_naming_style "%s_%d"
set_attribute hdl_array_generator "%s_%d"
set_attribute hdl_reg_naming_style "%s_reg%s"

in synthesis scripts but none of these fix the problems.

Is there a certain attribute related to module generate naming style that may fix the problem. Pls suggest.

Thanks for your time.