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memory LEC

WorldMaker

Hi all,

We always model the RAM as a flop in RTL simulation, can verplex LEC check the equivalence between the RAM RTL(shown below) and the RTL using verplex built-in RAM primitives?

/////////////Example/////////////////////////////////////////////////////

module mem2p (wclk,wadr,wdin,rclk,radr,rdout);

parameter adrbits=7;

parameter databits=8;

parameter adrmax = (1<<adrbits)-1;

input wclk;

input [adrbits-1:0] wadr;

input[databits-1:0] wdin;

input rclk;

input [adrbits-1:0] radr;

output[databits-1:0] rdout;

reg[databits-1:0] rdout;

reg[databits-1:0] mem[0:adrmax];

always @(negedge wclk) mem[wadr] = wdin;

always @(posedge rclk) rdout=mem[radr];

endmodule

 

 

thanks,

worldmaker

Parents

  • Hi Chrystian,

     

    I asked the same question in my other post, and I am still working on it. Actually it's not progressing smoothly due to my lacking experience in Conformal and especially in memory equivalence check. 

    Briefly, I want to check the equivalence between the golden RTL and the transistor-level schematic of a custom designed memory. The golden RTL consists of some interface logic, test logic and also a memory core which was shown above. 

    My trial solution is to divide it into 3 steps:

    1st:   build a new RTL, acutally a ram wrapper which is comprised of a conformal memory primitive, interface and test loigc. let's name it as bridge RTL tempororarily;

    2nd: equivalence check between the transistor-level schematic and the bridge RTL;

    3rd:  equivalence check between the bridge RTL and the golden RTL.

    I am still working on the 2nd and 3rd steps, and seems that I have not found out the right commands. Frankly, I wonder if Conformal can handle the 3rd step.

    thanks,

    Justin

     

Reply

  • Hi Chrystian,

     

    I asked the same question in my other post, and I am still working on it. Actually it's not progressing smoothly due to my lacking experience in Conformal and especially in memory equivalence check. 

    Briefly, I want to check the equivalence between the golden RTL and the transistor-level schematic of a custom designed memory. The golden RTL consists of some interface logic, test logic and also a memory core which was shown above. 

    My trial solution is to divide it into 3 steps:

    1st:   build a new RTL, acutally a ram wrapper which is comprised of a conformal memory primitive, interface and test loigc. let's name it as bridge RTL tempororarily;

    2nd: equivalence check between the transistor-level schematic and the bridge RTL;

    3rd:  equivalence check between the bridge RTL and the golden RTL.

    I am still working on the 2nd and 3rd steps, and seems that I have not found out the right commands. Frankly, I wonder if Conformal can handle the 3rd step.

    thanks,

    Justin

     

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