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verilog . D-latch with memory.

dvdeepak
Hi
can any one help me for the module and testbench of D-latch with memory.in this file attatched the figure has rd/wrd and clk are inputs and data is an inout. if rd/wrb is low then flip-flop is in write mode ;data are an input line;data on data line are written into latch when clk is positive. when rd/wrb is high , flip-flop is in read mode, data stored in latch are made available on data line..I tried alot but couldn't get it done.Please help.

Thanx.
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  • latch.v

    module latch (clk, rd, wr, d);
      input clk;
      input rd, wr;
      inout d;

      reg d_out;

      assign d = (rd && wr) ? d_out : 1'bz;

      always @(posedge clk) begin
        if (!rd && !wr)
          d_out = d;
      end
    endmodule

    test.v

    module test;
      reg clk = 0;
      reg rd, wr;
      reg d_in;
      wire d;

      latch i1 (clk, rd, wr, d);
      assign d = (!rd && !wr) ? d_in : 1'bz;

      always #5 clk = ~clk;

      initial begin
        @(negedge clk) rd = 0; wr = 0; d_in = 0;
        @(negedge clk) rd = 1; wr = 1; d_in = 0;
        @(negedge clk) rd = 0; wr = 0; d_in = 1;
        @(negedge clk) rd = 1; wr = 1; d_in = 1;
      end

      initial $monitor($time,,rd,,wr,,d);

    endmodule

    Tim

Reply

  • latch.v

    module latch (clk, rd, wr, d);
      input clk;
      input rd, wr;
      inout d;

      reg d_out;

      assign d = (rd && wr) ? d_out : 1'bz;

      always @(posedge clk) begin
        if (!rd && !wr)
          d_out = d;
      end
    endmodule

    test.v

    module test;
      reg clk = 0;
      reg rd, wr;
      reg d_in;
      wire d;

      latch i1 (clk, rd, wr, d);
      assign d = (!rd && !wr) ? d_in : 1'bz;

      always #5 clk = ~clk;

      initial begin
        @(negedge clk) rd = 0; wr = 0; d_in = 0;
        @(negedge clk) rd = 1; wr = 1; d_in = 0;
        @(negedge clk) rd = 0; wr = 0; d_in = 1;
        @(negedge clk) rd = 1; wr = 1; d_in = 1;
      end

      initial $monitor($time,,rd,,wr,,d);

    endmodule

    Tim

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