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Warnings when synthesis using RTL compiler

Greatrebel

 Hi All,

 

When I use RTL compiler to synthesis my design, I found there were a lot of warnings like

"The following sequential clock pins have no clock waveform driving them" and

"Referenced signal not in sensitivity list.  This may cause simulation mismatches between the original and synthesized designs." during elaboration.

 I am wondering whether these warnings are serious, can I ignore them.

 Thanks in advance

 

 

 

Parents

  •  Hi Greatrebel,

     I hope you realize that if the warnings were not meaningful, they probably would not be there. seq. clock pins is pretty bad since why would you have flops without clocks? Incomplete sensitivity list has minimal impact for synthesis but could lead to all sorts of issues for simulation. 

    good luck,

    gh-

Reply

  •  Hi Greatrebel,

     I hope you realize that if the warnings were not meaningful, they probably would not be there. seq. clock pins is pretty bad since why would you have flops without clocks? Incomplete sensitivity list has minimal impact for synthesis but could lead to all sorts of issues for simulation. 

    good luck,

    gh-

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