Warnings when synthesis using RTL compiler

 Hi Greatrebel,

 I hope you realize that if the warnings were not meaningful, they probably would not be there. seq. clock pins is pretty bad since why would you have flops without clocks? Incomplete sensitivity list has minimal impact for synthesis but could lead to all sorts of issues for simulation. 

good luck,

gh-

 hi grasshopper,

 I guess the warning "sequential clock pins have no clock waveform driving them" is caused by missing assignment to some registers in some case branches and using another signal for posedge. My code is something like below

assign clk_spi = cpol ^ cpha ^ sclk; //sclk is synchronise clk not system clk

   
always @ (posedge clk_spi or negedge rst)

if (!rst)
            begin
                bit_cnt <= #1 3'b0;
                byte_cnt <= #1 3'b0;
                state <= #1 `IDLE;
                spi_instr <= #1 8'b0;
                read_mem <= #1 `INST_WIDTH'b0;
            end

        else
            begin
                bit_cnt <= #1 next_bit_cnt;
                byte_cnt <= #1 next_byte_cnt;
                state <= #1 next_state;   
                spi_instr <= #1 next_spi_instr;
                read_mem <= next_read_mem;
            end

If I use system clk instead of clk_spi, it seems like the warnins gone.But I need that signal for those registers. So I can not have clockconstraint on those registers.

Hi Greatrebel,

the RTL without the timing constraints is not terribly helpful since I people cannot tell what or how you defined the clocks. Also note that for clock propagation purposes most synthesis tools do not use the logic function but instead the unateness of the cells as defined in the libraries.

 gh-

Hello Greatrebel,

I am facing the same "Sequential clock pins without clock waveform

The following sequential clock pins have no clock waveform driving them. No
timing constraints will be derived for paths leading to or from these pins" problem while synthesizing my RTL code.

Did you ever get around to fixing it?

Thanks
Azhar