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Warnings when synthesis using RTL compiler

Greatrebel

 Hi All,

 

When I use RTL compiler to synthesis my design, I found there were a lot of warnings like

"The following sequential clock pins have no clock waveform driving them" and

"Referenced signal not in sensitivity list.  This may cause simulation mismatches between the original and synthesized designs." during elaboration.

 I am wondering whether these warnings are serious, can I ignore them.

 Thanks in advance

 

 

 

Parents

  •  hi grasshopper,

     I guess the warning "sequential clock pins have no clock waveform driving them" is caused by missing assignment to some registers in some case branches and using another signal for posedge. My code is something like below

     

    assign clk_spi = cpol ^ cpha ^ sclk; //sclk is synchronise clk not system clk

       
    always @ (posedge clk_spi or negedge rst)

    if (!rst)
                begin
                    bit_cnt <= #1 3'b0;
                    byte_cnt <= #1 3'b0;
                    state <= #1 `IDLE;
                    spi_instr <= #1 8'b0;
                    read_mem <= #1 `INST_WIDTH'b0;
                end

            else
                begin
                    bit_cnt <= #1 next_bit_cnt;
                    byte_cnt <= #1 next_byte_cnt;
                    state <= #1 next_state;   
                    spi_instr <= #1 next_spi_instr;
                    read_mem <= next_read_mem;
                end

    If I use system clk instead of clk_spi, it seems like the warnins gone.But I need that signal for those registers. So I can not have clockconstraint on those registers.

Reply

  •  hi grasshopper,

     I guess the warning "sequential clock pins have no clock waveform driving them" is caused by missing assignment to some registers in some case branches and using another signal for posedge. My code is something like below

     

    assign clk_spi = cpol ^ cpha ^ sclk; //sclk is synchronise clk not system clk

       
    always @ (posedge clk_spi or negedge rst)

    if (!rst)
                begin
                    bit_cnt <= #1 3'b0;
                    byte_cnt <= #1 3'b0;
                    state <= #1 `IDLE;
                    spi_instr <= #1 8'b0;
                    read_mem <= #1 `INST_WIDTH'b0;
                end

            else
                begin
                    bit_cnt <= #1 next_bit_cnt;
                    byte_cnt <= #1 next_byte_cnt;
                    state <= #1 next_state;   
                    spi_instr <= #1 next_spi_instr;
                    read_mem <= next_read_mem;
                end

    If I use system clk instead of clk_spi, it seems like the warnins gone.But I need that signal for those registers. So I can not have clockconstraint on those registers.

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