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Warnings when synthesis using RTL compiler

Greatrebel

 Hi All,

 

When I use RTL compiler to synthesis my design, I found there were a lot of warnings like

"The following sequential clock pins have no clock waveform driving them" and

"Referenced signal not in sensitivity list.  This may cause simulation mismatches between the original and synthesized designs." during elaboration.

 I am wondering whether these warnings are serious, can I ignore them.

 Thanks in advance

 

 

 

Parents

  • Hi Greatrebel,

    the RTL without the timing constraints is not terribly helpful since I people cannot tell what or how you defined the clocks. Also note that for clock propagation purposes most synthesis tools do not use the logic function but instead the unateness of the cells as defined in the libraries.

     gh-

     

Reply

  • Hi Greatrebel,

    the RTL without the timing constraints is not terribly helpful since I people cannot tell what or how you defined the clocks. Also note that for clock propagation purposes most synthesis tools do not use the logic function but instead the unateness of the cells as defined in the libraries.

     gh-

     

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