Verilog simulation using verilog XL

 Hi,

i want to simulate a sample MUX21 realised on my schematic. I think, before going on the verilog XL , i need to put a load capacitor (classical cap) at the output to be able to see my output signal Z.

Then, arrived on the verilog XL interface, when i lauch the simulation, i have this following error:

*************************on the icfb terminal; *****************************************

\o ---------- Begin Netlist Configuration Info ----------
\o                 (incremental data only)
\o
\o CELL NAME                   VIEW NAME            NOTE            
\o ---------                   ---------            ----            
\o
\o cap                         symbol               *Stopping View* 
\o nsvtlp                      verilog              *Stopping View* 
\o psvtlp                      verilog              *Stopping View* 
\o MUX21                    schematic                            

******************************on the verilog XL terminal *************************************

 Message!  deleted TMS file 'verilog.tms' due to error in                       
          input file                                                           
                                                           [Verilog]

Error!    Module or primitive (cap) not defined            [Verilog-MOPND]     
          "ihnl/cds0/netlist", 19: cap C0(.MINUS(                              
          cds_globals.gnd_), .PLUS(Z));
1 error
End of Tool:    VERILOG-XL    08.20.001-p   Jun  9, 2010  15:03:34

****************************************************************

is the problem comes from to the view name of the capacity?  

thank you