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defined clocks not propagate

tompy

I have a design with clocks defined at root.I can use [get_attrbute  propagated_clocks] to get clock propagate at g152/Z,

however, I cannot get propagated clock at g151/Z

  XOR2D0HVT g151(.A1 (n_2), .A2 (clk2), .Z (clk2_inv));
  XOR2D0HVT g152(.A1 (n_2), .A2 (clk1), .Z (clk1_inv));

 I can also get propagated clock at g151/A2 and g152/A2

this is pretty weird since g151 and g152 are same logic, but I can't get propagated clock at g151 output!

can someone tell me why g151 block the clock propagation? thanks!

 

Parents

  •  Hi gh:

    g151 and g152 are synthesized result, not hand-instantiating. its RTL is:

      assign clk1_inv = (!scan_mode) ? !clk1 : clk1;
      assign clk2_inv = (!scan_mode) ? !clk2 : clk2;

     

    and synthesized result is 

      INVD0HVT g40(.I (scan_mode), .ZN (n_2));

      XOR2D0HVT g151(.A1 (n_2), .A2 (clk2), .Z (clk2_inv));
      XOR2D0HVT g152(.A1 (n_2), .A2 (clk1), .Z (clk1_inv));

     this is a huge design(10M+ gate counts), and the logic above is located at aaa/bbb/ccc/ddd/

    case1: If I extract ddd and directly create clock at clk1 and clk2, I can get propagated clocks at both g151 and g152

    case2: if I read in aaa and create clock at aaa input port clk1 and clk2, the issue I mentioned will occur.

    in case2 I try directly create clock at g151/A2 and g152/A2, for some reason, I still can only get propagated clock at g152/Z.

    I only read in netlist and create clock at clk1 and clk2, there is no other constraints, I did not set_case_analysis at scanmode port.

     thanks for the reply

    /tompy

Reply

  •  Hi gh:

    g151 and g152 are synthesized result, not hand-instantiating. its RTL is:

      assign clk1_inv = (!scan_mode) ? !clk1 : clk1;
      assign clk2_inv = (!scan_mode) ? !clk2 : clk2;

     

    and synthesized result is 

      INVD0HVT g40(.I (scan_mode), .ZN (n_2));

      XOR2D0HVT g151(.A1 (n_2), .A2 (clk2), .Z (clk2_inv));
      XOR2D0HVT g152(.A1 (n_2), .A2 (clk1), .Z (clk1_inv));

     this is a huge design(10M+ gate counts), and the logic above is located at aaa/bbb/ccc/ddd/

    case1: If I extract ddd and directly create clock at clk1 and clk2, I can get propagated clocks at both g151 and g152

    case2: if I read in aaa and create clock at aaa input port clk1 and clk2, the issue I mentioned will occur.

    in case2 I try directly create clock at g151/A2 and g152/A2, for some reason, I still can only get propagated clock at g152/Z.

    I only read in netlist and create clock at clk1 and clk2, there is no other constraints, I did not set_case_analysis at scanmode port.

     thanks for the reply

    /tompy

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