RTL Compiler: Manually Add Logic Gates

Hi,

Just an update.

I now have a solution - my previous problem was that I was confustion re pins/ports, and also not correctly making changes at the correct level of hierachy.

I would still be interested in comparing my solution with other scripts that may be available.

 Thanks,

Steven

Hi Steven,

as you indicated, I think there are many ways to skin the cat. I believe it really depends what your exact needs are:

+ using edit_netlist commands is perfectly adequate

+ for isolation in the context of power you could rely on CPF infrastructure which will do the insertion for you based on power constraints

+ for isolation in the context of DFT you could rely on the insert_dft command if it meets your needs. I believe your goal is one of 

   shadow logic support so check out the following command:

 c:/>  insert_dft shadow_logic -h
  insert_dft shadow_logic: inserts test logic to enable testing of shadow logic around a module

Usage: insert_dft shadow_logic [-around <instance>+] [-mode <string>] [-auto] [-minimum_shadow_logic_pins <integer>]
           [-exclude_shadow_logic <instance>+] [-balance] [-preview] [-dont_map] [-test_control <test_signal>] [-test_clock_pin <pin|port>]
           [-rise] [-fall] [-group <pin>+]+ [-exclude <pin>+] [-only <pin>+]

    [-around <instance>+]:
        instances around which DFT shadow logic must be inserted
    [-mode <string>]:
        mode of operation {no_share|share|bypass}
    [-auto]:
        automatic shadow logic insertion
    [-minimum_shadow_logic_pins <integer>]:
        inserts shadow logic on blackboxes with pins exceeding this value (default: 10)
    [-exclude_shadow_logic <instance>+]:
        exclude shadow logic around these instances
    [-balance]:
        group unmatched inputs/outputs to have a balanced number of groups
    [-preview]:
        show what would be done only, but do not modify the design
    [-dont_map]:
        do not techmap the inserted logic even though design is mapped
    [-test_control <test_signal>]:
        test signal used to control the DFT logic
    [-test_clock_pin <pin|port>]:
        use this clock pin to trigger control/observation flops
    [-rise]:
        use rising edge of test clock
    [-fall]:
        use falling edge of test clock
    [-group <pin>+]:
        what pins to observe together and/or control to the same value
    [-exclude <pin>+]:
        do not control/observe these pins
    [-only <pin>+]:
        only control/observe these pins

The nice thing about most insert_dft commands is they have a -preview option so you do not have to mangle your design and rerun to get it right. There are other insert_dft commands that may do what you want.

+ Finally there is insert_io_buffers for buffer-level isolation. This commands requires you to run 'include load_etc.tcl' to become accessible

Please post back and report your findings.

 regards,

gh-